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The ARM Cortex-A9 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor providing up to 4 cache-coherent cores. == Overview == (詳細はtitle=Cortex-A9 Processor Specifications )〕 * Out-of-order speculative issue superscalar execution 8-stage〔 pipeline giving 2.50 DMIPS/MHz/core. * NEON SIMD instruction set extension performing up to 16 operations per instruction (optional). * High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional). * Thumb-2 instruction set encoding reduces the size of programs with little impact on performance. * TrustZone security extensions. * Jazelle DBX support for Java execution. * Jazelle RCT for JIT compilation. * Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution. * L2 cache controller (0–4 MB). * Multi-core processing. ARM states that the TSMC 40G hard macro implementation typically operating at 2 GHz; a single core (excluding caches) occupies less than 1.5 mm2 when designed in a TSMC 65 nanometer (nm) generic process and can be clocked at speeds over 1 GHz, consuming less than 250 mW per core. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「ARM Cortex-A9」の詳細全文を読む スポンサード リンク
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